发明名称 Scan test circuit
摘要 The scan test circuit according to one embodiment of the present invention comprises a noninversion/inversion control circuit inserted and connected between a sequential circuit and a combinational circuit included in a path to be subjected to a scan test, the noninversion/inversion control circuit not inverting or inverting scan data output from said sequential circuit, on outside of said sequential circuit at arbitrary timing.
申请公布号 US2005138510(A1) 申请公布日期 2005.06.23
申请号 US20040761286 申请日期 2004.01.22
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 TERAZAWA TOSHIHIRO
分类号 G01R31/28;G01R31/3185;G06F11/22;H01L21/822;H01L27/04;(IPC1-7):G01R31/28 主分类号 G01R31/28
代理机构 代理人
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