Method and apparatus for logic analyzer observability of buffered memory module links

摘要

Some embodiments of the invention maintain a high degree of overall logic analysis and debug capabilities while simultaneously enabling the reduction of logic analyzer design complexity. Other embodiments of the invention provide a logical analyzer interface (LAI) mode of operation to memory module buffers by adding additional LAI features to the silicon designed to also operate in a normal mode. Other embodiments of the invention are described in the claims.