| 发明名称 |
Functional test design for testability (DFT) and test architecture for decreased tester channel resources |
| 摘要 |
According to one aspect of the present invention, multiple pins of a chip are connected to a single test channel of a tester. This allows an older tester with fewer test channels to be used with newer chips that have more pins than there are test channels.
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| 申请公布号 |
US2005138500(A1) |
申请公布日期 |
2005.06.23 |
| 申请号 |
US20030721474 |
申请日期 |
2003.11.25 |
| 申请人 |
SUL CHIMSONG;MURADALI FIDEL |
发明人 |
SUL CHIMSONG;MURADALI FIDEL |
| 分类号 |
G01R31/28;G01R31/3185;G01R31/319;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/28 |
| 代理机构 |
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