| 摘要 |
PROBLEM TO BE SOLVED: To provide a semiconductor memory device provided with a hierarchical bit line structure which can cope with high speed operation while suppressing increase of circuit area. SOLUTION: This semiconductor memory comprises a memory array; a pair of local bit lines corresponding to each memory array; a pair of global bit lines corresponding to the pair of local bit lines; a pre-charge circuit of which the output end is connected to the pair of local bit lines; a local write-amplifier circuit of which the input end is connected to the pair of global bit lines and the output end is connected to the pair of local bit lines; and a control signal line connected to input ends of the pre-charge circuit and the local write-amplifier circuit. The semiconductor memory is characterized in that the local write-amplifier circuit is made non-activated at the time of activation of the pre-charge circuit, and the pre-charge circuit is made non-activated at the time of activation of the local amplifier circuit. COPYRIGHT: (C)2005,JPO&NCIPI |
