发明名称 VERIFICATION SYSTEM
摘要 PROBLEM TO BE SOLVED: To achieve reduction in the load of a test verifier and the shortening of a test verification time. SOLUTION: This system comprises a random number generation means; a means for changing a waiting time depending on the value of a random number generated by the random number generation means; a clock output means for outputting at least two kinds of clocks; and an operation module operated by the clocks outputted by the clock output means. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005165747(A) 申请公布日期 2005.06.23
申请号 JP20030404665 申请日期 2003.12.03
申请人 CANON INC 发明人 SUZUKI YUICHIRO
分类号 G01R31/3183;G01R31/28;G06F17/50;(IPC1-7):G06F17/50;G01R31/318 主分类号 G01R31/3183
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