| 摘要 |
PROBLEM TO BE SOLVED: To solve the problem that it has been required to insert a circuit dedicated for tests separately from a normally operating circuit and to correct the circuit or adjust its timing so as to adapt to scan tests since it has been required to previously separate clip-flop circuits by the type of a clock to be used for scan tests on integrated circuits when a plurality of flip-flop circuits of different types of clocks are present in one integrated circuit and to separate conditioned reset signal. SOLUTION: A whole semiconductor integrated circuit using a single-phase clock or a flip-flop circuit unit 1 in a circuit block is previously provided with both an XOR gate 4 for switching between rising-edge and falling-edge clock inputs and a selector 7 for switching between reset inputs for normal operation and for tests. It is therefore possible to perform scan tests only at rising regardless of whether normal operation is rising or falling and eliminate the need for correction etc. of the circuit for tests. COPYRIGHT: (C)2005,JPO&NCIPI
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