| 摘要 |
In order to provide a semiconductor integrated circuit equipped with a clock distribution circuit that enables clock skew to be reduced without requiring great effort and without being affected by temperature variations or voltage variations, and a manufacturing method thereof, in a clock distribution circuit 1 installed in a semiconductor integrated circuit, part of the distribution path of a clock signal that passes from a first selector 11 of a first circuit block 10 that has many buffer stages via a first buffer stage 10 A is used, and a distribution path of a clock signal to a second buffer stage 20 A of a second circuit block 20 that has few buffer stages is constructed.
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