| 摘要 |
It is to form a memory access circuit comprising a memory, a clock generator for generating a reference clock signal, and a clock delay adjusting circuit for delaying the reference clock signal to create a delay clock signal. The clock delay adjusting circuit is a circuit for generating a plurality of delay clock signals of various delay value. The memory access circuit further comprises a test data generator for generating test data and a memory access test controller for supplying a memory writing test start signal in reply to the external synchronizing signal. The test data generator generates the test data in reply to the memory writing test start signal, writes the test data into the memory in synchronization with the reference clock, and supplies the write data corresponding to the test data in synchronization with the reference clock, and the memory access test controller reads the test data from the memory in synchronization with the delay clock signal, compares the read test data with the write data, and adjusts the memory access timing according to as a result of the comparison.
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