发明名称 Cache memory
摘要 A cache memory is configured by a CAM, comprising a CAM unit for storing a head pointer indicating the head address of a data block being stored, the pointer map memory for storing a series of connecting relationships between pointers indicating addresses of data constituting a block and starting from the head pointer, and pointer data memory for storing data located by an address indicated by the pointer. The capability of freely setting the connection relationship of pointers makes it possible to set a block size arbitrarily and improves the usability of a cache memory.
申请公布号 US2005138264(A1) 申请公布日期 2005.06.23
申请号 US20050046890 申请日期 2005.02.01
申请人 FUJITSU LIMITED 发明人 GOTO SEIJI
分类号 G06F12/08;(IPC1-7):G06F12/08 主分类号 G06F12/08
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