发明名称 INTEGRATED CIRCUIT DESIGNING DEVICE AND METHOD
摘要 PROBLEM TO BE SOLVED: To provide an integrated circuit designing device and method for designing it unnecessary to integrate a duplex circuit and a main body circuit even when optimization by logical synthesis is performed in LSI design. SOLUTION: This integrated circuit designing device is provided with: a storage device equipped with an RTL (Register Transfer Level) file having RTL descriptions including layering designation and a corresponding file showing the correspondence of the output ports of two modules to be layered corresponding to the layering designation; and an arithmetic processor for designing an integrated circuit in accordance with the RTL file. The arithmetic processor performs the layering of a circuit to be designed corresponding to the RTL file, and prepares an output port file showing the output ports of the layered module group constituting the circuit, and selects the output port on the basis of the output port file and the corresponding file, and investigates a logical gate constituting a path up to the selected output port. Thus, the design of an LSI can be performed by the integrated circuit designing device. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005165681(A) 申请公布日期 2005.06.23
申请号 JP20030403726 申请日期 2003.12.02
申请人 NEC CORP 发明人 KANAMARU SHIGESUKE
分类号 G06F17/50;H03K19/00;H03K19/003;(IPC1-7):G06F17/50 主分类号 G06F17/50
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