| 摘要 |
An arithmetic unit is provided which is capable of enhancing area efficiency while suppressing operating speed reduction. A third partial product adder (T 101 ) is divided into a high order part (T 101 a) including high-order 12 bits and a low order part (T 101 b) including low-order 33 bits. The high order part (T 101 a) and the low order part (T 101 b) are placed in different rows in a Wallace tree array. Particularly, the low order part (T 101 b) is placed in a middle row in the Wallace tree array. More specifically, the low order part (T 101 b) is placed right under a high order part (S 101 a) and right above a low order part (S 102 b). The high order part (T 101 a) is placed in the bottom row of the Wallace tree array. More specifically, the high order part (T 101 a) is placed right under a high order part (S 102 a).
|
