A system interface having a cache memory and directors. Each one of the directors includes a data pipe coupled between an input of such one of the directors. The data pipe includes a data pipe memory and a data pipe memory controller for controlling the data pipe memory. Each one of the directors includes microprocessor coupled to the data pipe memory controller. The system includes a switching network coupled to the cache memory to transfer data between the memory and: (a) the input of a selected one of the plurality of directors through the data pipe memory; (b) the microprocessor and the data pipe memory through the data pipe memory controller of a selected one of the plurality of directors; and (c) the microprocessor and the data pipe memory controller while by-passing the data pipe memory of a selected one of the plurality of directors.
申请公布号
WO2004095211(A3)
申请公布日期
2005.06.23
申请号
WO2004US05731
申请日期
2004.02.26
申请人
EMC CORPORATION;PORAT, OFER;CAMPBELL, BRIAN, K.;XU, YUJIE;BRUNO, ERIC, J.;WILSON, PAUL, C.
发明人
PORAT, OFER;CAMPBELL, BRIAN, K.;XU, YUJIE;BRUNO, ERIC, J.;WILSON, PAUL, C.