| 摘要 |
The present invention provides a metallization arrangement for a semiconductor structure ( 1 ) having a first substructure plane (M 1 ), preferably a first metallization plane; a second metallization plane (M 2 ) having a first and a second adjacent interconnect (LBA; LBB); a first intermediate dielectric (ILD 1 ) for mutual electrical insulation of the first substructure plane (M 1 ) and second metallization plane (M 2 ); and via holes (V) filled with a conductive material (FM) in the intermediate dielectric (ILD 1 ) for connecting the first substructure plane (M 1 ) and second metallization plane (M 2 ). A liner layer (L) made of a dielectric material is provided under the second metallization plane (M 2 ), which liner layer is interrupted in the interspace (O) between the first and second adjacent interconnects (LBA; LBB) of the second metallization plane (M 2 ). The invention likewise provides a corresponding fabrication method.
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