发明名称 |
METHOD AND APPARATUS FOR GENERATING AND CONTROLLING A QUADRATURE CLOCK |
摘要 |
Quadrature clock generating apparatus includes a multiplexer selecting one of a generated clock and a gated generated clock as a double clock in accordance with a halt multiplexer control. Divider circuitry provides an alignment signal corresponding to an inverted double clock divided by two. A recovery circuit recovers first and second clocks having a 90° phase difference from the double clock in accordance with the alignment signal. A halt circuit controls the halt multiplexer control to select the gated generated clock when the alignment signal matches a pre-determined clock level. The halt multiplexer control is clocked by the generated clock.
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申请公布号 |
US2005127974(A1) |
申请公布日期 |
2005.06.16 |
申请号 |
US20030733791 |
申请日期 |
2003.12.10 |
申请人 |
BERKRAM DANIEL A.;WYATT PERRY M. |
发明人 |
BERKRAM DANIEL A.;WYATT PERRY M. |
分类号 |
G06F1/06;G06F1/10;H03H11/16;H03K3/00;H03K3/02;H03K5/00;H03K5/15;H03L7/06;H03L7/18;(IPC1-7):H03K3/00 |
主分类号 |
G06F1/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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