| 摘要 |
PROBLEM TO BE SOLVED: To increase the operation speed by not only shortening delay of an internal clock relative to an external clock as much as possible but also eliminating a need of a clock CDK for dot interleaved data. SOLUTION: A signal processing circuit using an internal clock CK for respective circuits and a clock CKIN for dot interleaving, which has a half frequency of the internal clock CK, is taken as a unit, and a signal processor is constituted by cascading a plurality of signal processing circuits. Each signal processing circuit is provided with a PLL circuit which is configured so as to include a delay part for the internal clock CK in a loop and generates the clock in response to input of the clock CKIN from the outside. COPYRIGHT: (C)2005,JPO&NCIPI
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