发明名称 |
Extendable method for revising patterned microelectronic conductor layer layouts |
摘要 |
Within both a method for revising a patterned conductor layer and a system for revising the patterned conductor layer there is provided within each wiring layout record within a series of wiring layout records within a wiring layout database directed towards a series of microelectronic fabrications an unoccupied equivalent wiring location within which may be formed at least one optional wiring pattern. When there is designed within an unoccupied equivalent wiring location for a single wiring layout record within the series of wiring layout records at least one optional wiring pattern and an interconnect option to the at least one optional wiring pattern.
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申请公布号 |
US2005132315(A1) |
申请公布日期 |
2005.06.16 |
申请号 |
US20050044750 |
申请日期 |
2005.01.26 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
CHEN HSIAO-HUI;KUO CHENG-HSIUNG |
分类号 |
G06F9/45;G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F9/45 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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