| 摘要 |
<p>The invention relates to fast analogue-to-digital converters having differential inputs and a parallel structure, comprising at least one network of N series resistors with value r and a network of N comparators. According to the invention, in order to minimise the effect of parasitic capacitances from the resistor network on the comparator response time, the series resistor network receives a reference voltage (VH) and is traversed by a fixed current I0 and, in addition, the row i (i varying from 1 to N) comparator (COMPi) essentially comprises a dual differential amplifier with four inputs, namely: two inputs which receive a differential voltage VS-VN to be converted, a third input which is connected to a row i resistor of the network and a fourth input which is connected to a N-i row resistor of the network. The dual differential amplifier supplies a voltage representing a difference in form (VS-VSN) - (N-2i)r.I0, and the comparator switches in one direction or the other depending on the level of the voltage VS-VSN and the row i of the comparator when said difference changes sign.</p> |
