发明名称 |
Method for manufacturing gate structure for use in semiconductor device |
摘要 |
<p>The present invention provides a method for manufacturing a stacked-gate structure in a semiconductor device. The method includes the steps of sequentially forming a gate dielectric layer, a poly-silicon layer, a metal layer, a barrier layer and a tungsten layer on top of a semiconductor substrate, performing a rapid thermal annealing (RTA) process in a nitrogen ambient, forming a silicon nitride layer on top of the tungsten layer, and patterning the multilayer thin-film structure to form a predetermined configuration.</p> |
申请公布号 |
DE102004027067(A1) |
申请公布日期 |
2005.06.16 |
申请号 |
DE20041027067 |
申请日期 |
2004.06.03 |
申请人 |
NANYA TECHNOLOGY CORPORATION, KUEISHAN |
发明人 |
HO, TZU-EN;WU, CHANG-RONG;CHEN, YI-NAN;WU, KUO-CHIEN |
分类号 |
H01L21/28;H01L21/336;H01L29/49;H01L29/51;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/28 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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