| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a phase frequency comparator capable of enhancing the operating frequency of a PLL circuit. <P>SOLUTION: At the time of comparing the phase or frequency of an input clock signal consisting of the essential reference clock signal Sref and the feedback clock signal Sdiv of a PLL circuit, frequency of these clock signals Sref and Sdiv is divided by 1/N to produce frequency division clock signals Sref2 and Sdiv2. When the timing difference of two input clock signals Sref and Sdiv exceeds a predetermined level, these two input clock signals Sref and Sdiv are switched to the frequency division clock signals Sref2 and Sdiv2 and they are compared. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
