发明名称 |
Recessed gate structure with reduced current leakage and overlap capacitance |
摘要 |
A gate structure and method for forming the same the method including providing a silicon substrate including one of N and P-well doped regions and an overlying the CVD silicon oxide layer; forming an opening in the CVD silicon oxide layer to include a recessed area extending into a thickness portion of the silicon substrate; thermally growing a gate oxide over exposed silicon substrate portions of the recessed area; backfilling the opening with polysilicon; planarizing the polysilicon to the opening level to reveal the silicon oxide layer; and, selectively removing the silicon oxide layer to form a recessed gate structure.
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申请公布号 |
US2005127433(A1) |
申请公布日期 |
2005.06.16 |
申请号 |
US20030728967 |
申请日期 |
2003.12.04 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
LIN DA-WEN;SHEU YI-MING;LEUNG YING-KEUNG |
分类号 |
H01L21/336;H01L29/423;H01L29/76;H01L29/78;(IPC1-7):H01L29/76 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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