VORRICHTUNG ZUM PARALLELEN PRÜFEN VON HALBLEITERSCHALTKREISEN

摘要

A novel system and method for testing semiconductor devices has a pattern generator implementing a test signal algorithm uniquely coupled with a recording system which is an individual hardware system for each device under test. The improved pattern generator and recording system functions in conjunction with a system designed to perform parallel test and burn-in of semiconductor devices, such as the Aehr Test MTX System. The MTX can functionally test large quantities of semiconductor devices in parallel. It can also compensate for the appropriate round trip delay value for each chip select state for each device under test. This system of testing provides an effective and practical method for reducing overall test cost without sacrificing quality.