发明名称 Bit line reference circuits for binary and multiple-bit-per-cell memories
摘要 Auto-tracking bit line reference schemes generate a "½ cell current" reference by programming reference cells to threshold voltages that are between threshold voltage levels used to represent data. A common word line can control both a selected memory cell and a reference cell to provide a reference current, and differential sense amplifiers can compare a bit line current to reference currents to thereby distinguish data values. Current through other reference cells can be mirrored to pull-up devices to further improve the tracking of the reference line and bit line currents. Embodiments of the invention can be used with binary and multiple-bit-per-cell memories and with a variety of memory array architectures and memory cell structures.
申请公布号 US6906951(B2) 申请公布日期 2005.06.14
申请号 US20020173468 申请日期 2002.06.14
申请人 MULTI LEVEL MEMORY TECHNOLOGY 发明人 WONG SAU CHING
分类号 G11C11/56;(IPC1-7):G11C16/04;G11C14/00;G11C16/06;G11C7/00;G11C7/02 主分类号 G11C11/56
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