发明名称 Reducing transitions on address buses using instruction-set-aware system and method
摘要 An instruction-set-aware method for reducing transitions on an irredundant address bus comprises receiving a first address for communication to a memory on an irredundant address bus. The method retrieves an instruction from a memory location indicated by the first address, transmits the instruction on a data bus, and determines a category of the instruction. The method predicts a second address based, at least in part, on the first address, the instruction, and the category of the instruction.
申请公布号 US6907511(B2) 申请公布日期 2005.06.14
申请号 US20030342418 申请日期 2003.01.14
申请人 UNIVERSITY OF SOUTHERN CALIFORNIA 发明人 FALLAH FARZAN;AGHAGHIRI YAZDAN;PEDRAM MASSOUD
分类号 G06F12/02;(IPC1-7):G06F12/00 主分类号 G06F12/02
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