| 摘要 |
It is possible to realize high-speed packet identification while suppressing the circuit size. A reference table (11) contains a plurality of reference data sets (11a), (11b),..., (11n) each divided into unit data for each attribute and stored in an address storage area predetermined for each attribute. When a read out address is input, a plurality of unit data of the attribute corresponding to the read out address are output. An analysis circuit (12) analyzes an attribute of data to be compared in a packet which has been input. An address control circuit (13) outputs to the reference table (11) as a read out address an address corresponding to the attribute of the data-to- be-compared which has been analyzed by the analysis circuit. A plurality of unit comparison circuits (14a), (14b),..., (14n) are arranged to correspond to the plurality of reference data sets (11a), (11b),..., (11n). The plurality of unit data output from the reference table (11) are compared to the data-to-be-compared which has been analyzed by the analysis circuit (12). |
