| 摘要 |
In one embodiment, a semiconductor device (10) has a highly doped layer (26) having a first conductivity type uniformly implanted into a semiconductor substrate (20), where a channel region (28) is located between a top surface of the substrate (20) and the highly doped layer (26). In an alternate embodiment, a semiconductor device (70) has a counterdoped channel (86) and an anti- punch through region (74) below the channel. A gate stack (32) is formed over the substrate (20). A source (52) and drain (54, 53) having a second conductivity type are implanted into the substrate. The resulting non- volatile memory cell provides a low natural threshold voltage to minimize threshold voltage drift during a read cycle. In addition, a halo region (46), having the second conductivity type and implanted at an angle in the drain side, may be used to assist in hot carrier injection which allows a higher programming speed.
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