| 摘要 |
The processor issues instructions including a branch instruction under a first identifier (ID=0) and speculatively executes the instructions by branch prediction. In the event of the detection of a branch error, the processor issues instructions in the correct direction under a second identifier (ID=1) subsequently to the erroneously issued instructions. After the completion of all the instructions prior to the branch error, the processor cancels the instructions erroneously issued by branch prediction to resume the issuance of instructions in the correct direction. The processor updates the identifiers (IDs) attached to the instructions after the occurrence of a branch error. This allows the processor to issue instructions in the correct direction without waiting for the completion of all the instructions prior to the branch instruction that caused the branch error, thus ensuring enhanced processing performance. Moreover, the processor needs only at least two identifiers to be attached to the instructions. This allows reduction in hardware volume.
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