| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a power-on reset circuit capable of outputting a normal reset signal even when the rise of a power supply voltage is slow. <P>SOLUTION: A node NX is connected to a ground level GND via an NMOS 11 whose gate is fixedly connected to the ground level GND and further connected to a power line 10 via a MOS capacitor 12 formed by connecting the drain and source of a PMOS in common. Thus, even when the rise of a power supply voltage VD is slow at power application, the level VX of the node NX rises nearly following the power supply voltage VD. When the power supply voltage VD reaches a prescribed power supply potential VDD, the level VX gradually decreases by the off-leak current of the NMOS 11. Since inverters 13 to 15 operable by the power supply voltage VD are connected to the node NX, a reset signal POR output from the inverter 15 becomes "H" when the level VX decreases down to a half the power supply voltage VD. <P>COPYRIGHT: (C)2005,JPO&NCIPI</p> |
