发明名称 SCAN TEST CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To provide a scan test circuit capable of improving the failure detection ratio of a circuit including a plurality of latches, without causing the scale of this circuit to increase. <P>SOLUTION: This scan test circuit is applied to a circuit including a plurality of latches whose data input terminals are connected to data lines, and provided with flip flops for control whose scan chains are configured in a scan test, a first gate circuit for control which outputs data to be supplied via the data line in a normal operation, and outputs data to be set in the flip flops for control in a scan test, and supplies the data to the plurality of latches and a second gate circuit for control which sets the plural latches into through-states in the scan test. The plurality of latches are divided into at least two groups, and the plurality of latches included in each of those groups are respectively provided for each flip flop for control. <P>COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005148837(A) 申请公布日期 2005.06.09
申请号 JP20030381382 申请日期 2003.11.11
申请人 KAWASAKI MICROELECTRONICS KK 发明人 OKAMAE MICHINORI
分类号 G01R31/28;G06F11/22 主分类号 G01R31/28
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