发明名称 |
Integrated circuit package and method |
摘要 |
An integrated circuit package ( 60 ) has a substrate ( 12 ) with a first surface ( 51 ) for mounting a semiconductor die ( 20 ) and a second surface ( 52 ) defining a via ( 70 ). A lead ( 26 ) is formed by plating a conductive material to project outwardly from the second surface. The conductive material extends from the lead through the first via for coupling to the semiconductor die. |
申请公布号 |
US2005121767(A1) |
申请公布日期 |
2005.06.09 |
申请号 |
US20050040334 |
申请日期 |
2005.01.24 |
申请人 |
CELAYA PHILLIP C.;DONLEY JAMES S.;ST. GERMAIN STEPHEN C. |
发明人 |
CELAYA PHILLIP C.;DONLEY JAMES S.;ST. GERMAIN STEPHEN C. |
分类号 |
H01L23/14;H01L23/498;H05K3/24;H05K3/34;(IPC1-7):H01L21/44;H01L23/52 |
主分类号 |
H01L23/14 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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