发明名称 |
Data element size control within parallel lanes of processing |
摘要 |
Within a SIMD processor 2 data processing instructions are provided which specify parallel lanes of processing to be performed upon respective data elements. The data elements are permitted to vary in size whilst the number of processing lanes remain constant. Thus, the destination register size for a multiplication may be double the source register size. |
申请公布号 |
US2005125631(A1) |
申请公布日期 |
2005.06.09 |
申请号 |
US20040889471 |
申请日期 |
2004.07.13 |
申请人 |
ARM LIMITED |
发明人 |
SYMES DOMINIC H.;FORD SIMON A.;KERSHAW DANIEL;SEAL DAVID J. |
分类号 |
G06F9/30;G06F9/302;(IPC1-7):G06F15/00 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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