| 摘要 |
PROBLEM TO BE SOLVED: To improve electric characteristics and process stability by suppressing the deterioration of degree of margin of deviation in the mating of lithography treatment of an interlayer wiring structure accompanied by a detailed circuitry designing rule. SOLUTION: The Al-Cu film 12 of a lower layer side wiring layer and the TiN film 13 of a barrier metal are formed on a silicon substrate 11 and the d-TEOS film 15 of an interlayer insulating film is formed thereon as an interlayer wiring layer 14 to bury W plugs 16a, 16b and flatten them. A TiN film 17, an Al-Cu film 18 and a TiN film 19 are formed as an upper layer side wiring layer and patterning is applied thereon. In this case, etching is effected so as to be deeper than the surface of the interlayer wiring layer 14 by a dropping size (f) to form a dropping part P. According to this method, a margin can be kept in the depthwise direction by a size (f) when the deviation of mating A exists whereby an insulating distance can be secured. COPYRIGHT: (C)2005,JPO&NCIPI |
