发明名称 |
Reference cell configuration for a 1T/1C ferroelectric memory |
摘要 |
A reference cell layout for use in a 1T/1C ferroelectric memory array includes a transistor of a first polarity type having a gate coupled to a reference word line and a current path coupled between a bit line and an internal cell node, a transistor of a second polarity type having a gate coupled to a pre-charge line and a current path coupled between a source of power supply voltage and the internal cell node, a shunt reference word line extending across the reference cell that is electrically isolated from the reference word line, the pre-charge line and the transistors within the physical boundary of the memory cell, and a ferroelectric capacitor coupled between the internal cell node and a reference plate line.
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申请公布号 |
US2005122765(A1) |
申请公布日期 |
2005.06.09 |
申请号 |
US20040993202 |
申请日期 |
2004.11.18 |
申请人 |
ALLEN JUDITH E.;WILSON DENNIS R.;KRAUS WILLIAM F.;LEHMAN LARK E. |
发明人 |
ALLEN JUDITH E.;WILSON DENNIS R.;KRAUS WILLIAM F.;LEHMAN LARK E. |
分类号 |
G11C11/22;(IPC1-7):G11C11/22 |
主分类号 |
G11C11/22 |
代理机构 |
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地址 |
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