SEMICONDUCTOR MEMORY HAVING SELF-TIMING CIRCUIT

摘要

A self-timing circuit (61) of a semiconductor memory comprising a dummy bit line (XDBL1) having self-timing dummy memory cells (SDMC 11,12) set to a first state and load dummy memory cells (LDMC 11,12) set to a second state opposite to the first state; a dummy bit line (XDBL2) having self-timing dummy memory cells (SDMC 21,22) set to a third state and load dummy memory cells (LDMC 21,22) set to a forth state identical to the third state; and a timing control circuit (62) for delaying and outputting a self-timing signal (SLF) by a period corresponding to a difference in change speed between the potentials of the dummy bit lines (XDBL1,XDBL2).