| 摘要 |
PROBLEM TO BE SOLVED: To provide a phase transition memory which can realize low power consumption while a chip size is reduced. SOLUTION: The phase transfer memory comprises a plurality of memory cells including a phase transition layer 20 formed on a semiconductor substrate 25 to generate amorphous-crystal phase transition, an electrode layer 31 formed on the phase transition layer 20, a memory cell array 11 in which the memory cells are allocated in the form of a matrix, a word line for connecting in common the memory cells of the same row, and a bit line electrically connected to the electrode layer 31 for connecting in common the phase transition layer 20 of the memory cells of the same column. The phase transition layer 20 includes a first region 28 in contact with the semiconductor substrate 10 for each memory cell, and a second region 29 for connecting in common the first region 28 among a plurality of memory cells of the same column. The electrode layer 31 is formed on the second region 28, and the area in contact between the first region 28 and the semiconductor substrate 10 is smaller than the area in contact between the second region 28 and electrode layer 31. COPYRIGHT: (C)2005,JPO&NCIPI |
