| 摘要 |
PROBLEM TO BE SOLVED: To optimally arrange a plurality of blocks for minimizing excess of delay time, in short processing time. SOLUTION: Inputting means 6 input information about a logic circuit having a hierarchy of a plurality of blocks, and RTL estimating means 7 calculate a delay time in the blocks first. Path detecting means 8 detect a timing path routed through the plurality of blocks, and delay calculating means 9 calculate a delay value on the assumption that a wire length between the blocks is zero. Delay margin setting means 10 subtract the delay value from a predetermined delay time to set a delay margin. The delay margin provides an objective function as a weight on a virtual wire length of each terminal pair between the blocks in a arrangement process. The blocks are arranged automatically with the objective function. COPYRIGHT: (C)2005,JPO&NCIPI
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