| 摘要 |
<p>1,004,019. Automatic character reading. SIEMENS & HALSKE A.G. April 13, 1964 [April 11, 1963], No. 15100/64. Heading G4R. Defects in the printed character cause gaps in the signals as shown in Fig. 2, which are removed (Fig. 3) by the circuit of Fig. 8. The input signals on line n are gated in gate GS 11 with the same signal delayed by a one-bit store SS1. The output is passed, via one-bit store SS11 to one input of blocking gate GS110, the blocking input of which is from line n. Output of gate GS110 passes, via Or gate OGS, to one-bit store S1S110. The input n is also applied to this gate. The output of gate GS110 is also applied, via one-bit store S1v to blocking gate GS1v0 and the output is the blocking input of gate IS1v0. During scanning of column n-2, Fig. 1, the first black is in row m-2. The corresponding signal on line n passes through Or gate OGS and, after a delay of one-bit appears at the output of store S1S110 passing through blocking gate TS1v0 to output w. The black signal from line n produces an output from gate GS11 as there are black signals at points m-2 and m-1. When the scanning spot reaches row m a white signal is produced so that gate GS110 opens, allowing the output from store SS11 to pass via Or gate OGS to store " 1 " in S1S110 ready to take the place of the white signal on line n. If the next signal is black (as in Fig. 1) gate GS1v0 is blocked, giving no output and allowing gate TS1v0 to pass the signal from store S1S110 to output w. The white area in row m of scan n-z is filled in, therefore, by the detection of a " 110 " sequence of which the "0 " is transmitted as a " 1 " if it is followed by a " 1." If it is not followed by a " 1 " signal, a " 0 " is transmitted. Other possible rules are suggested, e.g. that the replacement of a " 0 " by a " 1 " may depend upon being preceded by a group of black signals longer than " 11 " or upon being followed by a black signal somewhere within a larger group of following signals. Breaks in the perpendicular direction as shown in Fig. 4 are filled by a circuit, Fig. 10, having a shift register RZ1 1 which holds a complete column of signals. Corresponding signals from adjacent columns are gated by gate GZ11 and the output entered into another register RZ 11. The presence in three adjacent columns of " 1," " 1 " and " 0 " in the same row is detected by blocking gate GZ110. A following " 1 " in the next column blocks gate GZ1v0 so that output gate TZ1v0 is unblocked at the time the " 110 " signal appears at the output of a further one-column shift register R1Z110. By this means the blank column n in Fig. 5 resulting from the break in the character is filled to produce the signals of Fig. 6. Circuits for filling spaces in a column and for filling spaces across the columns may be combined, a suitable delay being provided to compensate for the different storage periods of the two component circuits.</p> |
