PARALLEL PROCESSING INTEGRATED CIRCUIT TESTER

摘要

An integrated circuit tester includes several processing nodes, one node associated with each terminal of an integrated circuit device under test (DUT). At precisely determined times, each node generates and transmits a test signal to the associated DUT terminal or samples a DUT output signal produced at the DUT terminal. Each node includes memory for storing algorithmic instructions for generating a set of commands indicating when a test signal is to be transmitted to the associated terminal and indicating when a DUT output at the associated node is to be sampled. Each node also includes a processor for processing the algorithmic instructions to produce the commands. Each node further includes circuits responsive to the commands for transmitting the test signals to the associated DUT terminal and for sampling the DUT output signal produced at the associated DUT terminal at times indicated by the commands. The processing nodes are interconnected in serial fashion to form a network for conveying the algorithmic instructions to the memory of each node and for conveying signals for synchronizing operations of the processing nodes. The nodes contain circuitry to start and stop operations in a unified manner so that the serially connected nodes act as if connected in parallel.