发明名称 |
Clock distribution system |
摘要 |
A data processing architecture comprising: an input device for receiving an incoming stream of data packets; and a plurality of processing elements which are operable to process data received thereby; wherein the input device is operable to distribute data packets in whole or in part to the processing elements in dependence upon the data processing bandwidth of the processing elements. |
申请公布号 |
GB2389689(B) |
申请公布日期 |
2005.06.08 |
申请号 |
GB20030019801 |
申请日期 |
2002.02.14 |
申请人 |
* CLEARSPEED TECHNOLOGY LIMITED;* CLEARSPEED SOLUTIONS LIMITED;* CLEARSPEED TECHNOLOGY PLC |
发明人 |
IAN * SWARBRICK;DAVID * WILLIAMS |
分类号 |
G06F13/36;G06F1/10;G06F17/50;H04L12/28;H04L12/56;(IPC1-7):G06F1/10 |
主分类号 |
G06F13/36 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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