Improvements in or relating to electronic circuits

摘要

1,108,861. Selective signalling; statistical apparatus. COMPAGNIE DE SAINT-GOBAIN. 5 April, 1965 [3 April, 1964], No. 14355/65. Headings G4A and G4H. [Also in Division H3] A logic element comprises a transistor (Fig. 1) having collector and emitter resistors R, R1 (preferably equal) and two equal input resistors r, connected to the base, of lesser value than the collector and emitter resistors, whereby if signals having binary levels approximately equal to the collector and emitter supplies are applied to the inputs, the output at the collector has one value if the signals are the same and another if they are different. Thus if point M is at half the supply potential 2V, two signals of - V at A and B will cause the transistor to be non-conductive so that the output Vc is zero. If the two signals are respectively +V and -V, the transistor will conduct giving a value of Vc which is preferably half the supply potential and if the two signals are both +V the base will be approximately at the collector supply potential and again the Vc will be approximately zero. Alternatively, if signals having binary levels equal to the supply potential and O are applied between A and B and earth, a voltage Vc appears only if the two signals are different. Thus, the circuit performs an " exclusive OR " or the equivalent parity function, depending on the sense of the logic. An OR function is also available at the emitter. The higher valued signal applied to the input need not be equal to the supply potential and a figure of 4/ 5 tbs of this value is used in the signal supply circuits of Fig. 8 (not shown) and Fig. 7. A phase comparator may be formed from the circuit by applying an A.C. reference voltage to one input and the input signal, after amplitude limitation, to the other. No output is produced if the signals are in phase and a maximum output voltage appears if they are 180 degrees out of phase. Signals in between produce a mean signal of lesser value (Fig. 3, not shown). If one input terminal is connected to earth the complement of a signal applied to the other is obtained and by using a number of such arrangements the complement of a binary number can be produced (Fig. 2, not shown). Binary numbers may be converted to their reflected form by using one of the logic elements to compare each adjacent pair of digits of the binary number, outputs of the logic elements providing the reflected number (Fig. 4, not shown). Reflected binary numbers may be converted to normal binary numbers by feeding each reflected digit to a respective logic element together with the output of the logic circuit associated with the next reflected digit (Fig. 5, not shown). A binary adder stage (Fig. 6) is formed from two of the logic elements together with a circuit marked " if." This latter element is as described in Specification 1,107,466 and connects one or other of the inputs to the output depending on the value of a command signal. The circuit of such a stage is illustrated in Fig. 7. The digits to be added are applied at an and b n to a logic element C1 according to the invention provided with two cascaded transistor output amplifiers. This supplies the command signal to the two bases of the " if " circuit and also one input of the sum circuit C2. The carry from the preceding circuit is one input of the " if " circuit and is represented by a switch providing the signal R n-1 The other input is the digit an. The carry forward is supplied at R n . Binary numbers may be compared for equality by feeding each corresponding digit to a respective one of the logic elements according to the invention operating as a parity checker and feeding the outputs to a " AND " circuit. They may alternatively be compared to find if one is bigger than the other by determing the algebraic function A + B and inspecting the carry figure. A suitable circuit is illustrated in Fig. 6 and this uses two of the logic circuits as parity checkers to control which of the two input terminals of an " if " circuit is connected to the respective output.