发明名称 Controlling cache memory in external chipset using processor
摘要 The present invention is a method and apparatus to control cache. A processor cache unit processes a cache access request from a processor core of a processor. The processor cache unit includes a processor cache controller and a processor cache. A chipset cache controller controls a chipset cache located in a chipset in response to the cache access request from the processor core. The chipset is coupled to the processor via a bus.
申请公布号 US6904499(B2) 申请公布日期 2005.06.07
申请号 US20010822643 申请日期 2001.03.30
申请人 INTEL CORPORATION 发明人 FANNING BLAISE B.
分类号 G06F12/08;(IPC1-7):G06F12/08 主分类号 G06F12/08
代理机构 代理人
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