发明名称 |
ESD protection circuit for mixed-voltage I/O ports using substrated triggering |
摘要 |
An ESD protection circuit for mixed-voltage input/output (I/O) circuits. The ESD protection circuit utilizes substrate triggering of a parasitic NPN BJT under a cascaded NMOS transistor pair with a current generated by a triggering current generator. The ESD protection circuit is triggered much faster. Under normal circuit operations, the triggering current generator can also endure high-voltage signals without overstressing internal components and retains good reliability.
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申请公布号 |
US6903913(B2) |
申请公布日期 |
2005.06.07 |
申请号 |
US20020253643 |
申请日期 |
2002.09.25 |
申请人 |
TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD. |
发明人 |
KER MING-DOU;CHUAN CHIEN-HUI |
分类号 |
H01L23/60;H01L27/02;H02H3/22;(IPC1-7):H02H3/22 |
主分类号 |
H01L23/60 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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