发明名称 |
Logic gate identification based on hardware description language circuit specification |
摘要 |
Techniques are disclosed for estimating the signal propagation delays within a circuit, based on a description of the circuit written in a hardware description language (HDL), such as a register transfer language (RTL). Assignment statements in the description which describe the performance of a logical function are modeled using logic gates which perform the function described. A particular function may be modeled using one or more logic gates depending on the number of inputs to the function. The delay associated with performance of the function is estimated by estimating the delay through the circuit used to model the function. Estimates for multiple functions may be combined to estimate the total delay associated with a particular signal path through a circuit.
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申请公布号 |
US6904573(B1) |
申请公布日期 |
2005.06.07 |
申请号 |
US20030446097 |
申请日期 |
2003.05.27 |
申请人 |
HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. |
发明人 |
BURDEN DAVID |
分类号 |
G06F17/50;(IPC1-7):G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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