Variable layout design for multiple voltage applications

摘要

An integrated circuit it comprises a logic cell. The logic cell is without nwell contacts and comprises top and bottom voltage supply wires. The integrated circuit also comprises a first filler cell comprising top and d bottom voltage supply wires and an nwell region coupled to the bottom voltage supply wire. The integrated circuit further comprises a second filler cell with an nwell region coupled to a top voltage supply wire. The integrated circuit still further comprises a third filler cell comprising top and bottom voltage supply wires. The third filler cell also comprising a pair of nwell regions. One of nwell regions is coupled to the top voltage supply wire and the other nwell region is coupled to the bottom voltage supply wire. The standard cell and the filler cells each comprise a PRboundary overlapping a top portion of the nwell region in each cell by a first distance.