发明名称 HIGH-SPEED MEMORY ACCESS CONTROL DEVICE
摘要 PROBLEM TO BE SOLVED: To cut processing time in burst access of high speed storage such as SDRAM which operates at high speed, and to avoid increase of a circuit scale. SOLUTION: An high-speed memory access control device determines that an exceptional access over 2 pages is required by an address burst number determination circuit 111 with an exception access determination flag ext_acs based on an access start address BMA and a burst length signal BRST, and performs processing to output the number of access word for each page by a pre-burst signal PREBRST and a post-burst signal POSTBRST before start of access sequence of SDRAM3. When a start address determination circuit 132 determines that the number of a start column address COLA is odd, the high-speed memory access control device changes the start column address into the front even number in an address control circuit 14, and controls timing of a data mask enable signal DQM so as to access only the specified number of word from the start column address of an odd number. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005141682(A) 申请公布日期 2005.06.02
申请号 JP20030380272 申请日期 2003.11.10
申请人 DIGITAL ELECTRONICS CORP 发明人 SHINHAN TETSUO
分类号 G06F12/02;(IPC1-7):G06F12/02 主分类号 G06F12/02
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