INFORMATION PROCESSOR AND BUS CONTROL DEVICE

摘要

PROBLEM TO BE SOLVED: To inexpensively and reliably attain high performance and responsiveness as to a common bus, an information processor connected to other information processors through a common memory connected to the common bus and capable of taking charge of part of prescribed distributed processing and a bus control device for suitably imparting the use right of the common bus to each of these information processors. SOLUTION: Each information processor is provided with: an interface means for interfacing the common bus connected to the common memory and a plurality of information processors; a monitoring means for monitoring the frequency of access to each storage area of the common memory through the interface means and the common bus; and a control means for preferentially storing contents stored in a storage area having high access frequency out of storage areas of the common memory into a cache used for access to the common memory. COPYRIGHT: (C)2005,JPO&NCIPI