| 摘要 |
PROBLEM TO BE SOLVED: To enhance the effective speed of access to a cache memory by reducing a time required for control inside a data transfer integrated circuit without increasing the bus width of the cache memory. SOLUTION: A disk control device 20 comprises a CPU 30, a plurality of channel control parts 40, a plurality of disk control parts 50, a cache memory 70, and a data transfer integrated circuit communicably connected to the cache memory 70 by a plurality of data buses. When receiving a request to access the cache memory 70 from the CPU 30, the channel control parts 40 and the disk control parts 50, the data transfer integrated circuit 20 accesses the cache memory 70 while using the data buses whose number is determined according to the length of transfer data set in the access request. COPYRIGHT: (C)2005,JPO&NCIPI
|
