发明名称 |
MEMORY CONTROL UNIT AND MEMORY CONTROL METHOD |
摘要 |
<P>PROBLEM TO BE SOLVED: To obtain a memory control unit facilitating cache management of data stored in a memory. <P>SOLUTION: The cache management of processing data in the memory can be performed easily by controlling using an upper-level counter incrementing each time a block counter exceeds a number storable in the memory, in addition to the block counter incrementing at the time one block is completed in each processing means. Also, with the provision of an error correction result decision circuit, control signal generation for permitting the operation of each processing is masked when error correction cannot be performed. <P>COPYRIGHT: (C)2005,JPO&NCIPI |
申请公布号 |
JP2005141341(A) |
申请公布日期 |
2005.06.02 |
申请号 |
JP20030375092 |
申请日期 |
2003.11.05 |
申请人 |
HITACHI LTD;HITACHI-LG DATA STORAGE INC |
发明人 |
IKEDA MASAKAZU;HIRABAYASHI MASAYUKI |
分类号 |
G06F12/16;G06F3/06;G11B20/10;G11B20/18 |
主分类号 |
G06F12/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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