发明名称 BYPASS TECHNIQUE OF PIXEL CLOCK GENERATING CIRCUIT AND CRT CONTROL CIRCUIT IN IMAGE CONTROL INTEGRATED CIRCUIT
摘要 PROBLEM TO BE SOLVED: To provide a method for providing a video data stream at a clock rate independent of a pixel clock rate in a video processor unit. SOLUTION: In the method, an inherent video data is received from a video source at an inherent clock rate, the video data is stored in a storage, a selected portion of the video data is read at a memory clock rate, the selected portion of the video data is rasterized, the rasterized video data is packetized, and the packetized video data is transmitted to a display unit through a link at a link rate based on the memory clock rate. COPYRIGHT: (C)2005,JPO&NCIPI
申请公布号 JP2005143087(A) 申请公布日期 2005.06.02
申请号 JP20040271125 申请日期 2004.09.17
申请人 GENESIS MICROCHIP INC 发明人 KOBAYASHI OSAMU
分类号 G09G3/36;G06F3/14;G09G3/20;G09G5/00;G09G5/06;G09G5/395;H04N5/00;H04N5/44;H04N5/66;H04N7/12;H04N7/173;H04N21/431 主分类号 G09G3/36
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