发明名称 SYSTEM AND METHOD FOR CONTROLLING A PROCESSOR INCLUDING A DIGESTER UTILIZING TIME-BASED ASSESSMENTS
摘要 A system for controlling a processor having at least one sampling port connected to a stage of the processor in order to sample a reactant product from the processor. The system includes a controller configured to control a processing parameter of the processor based on measurements of at least one property of the reactant product such that changes to the processing parameter maintain a target value for the at least one property of the reactant product. The system further includes a dead time compensator. The dead time compensator is configured, based upon a prescribed dead time related to a time before at least one effect of at least one change to the processing parameter is fully realized, to evaluate the reactant product to determine if the effect has been realized at a plurality of sequential times offset from the dead time. 2R
申请公布号 WO2005019526(A3) 申请公布日期 2005.06.02
申请号 WO2004US13001 申请日期 2004.05.07
申请人 METSO AUTOMATION USA, INC.;LAMPELA, KARI, JUHANI 发明人 LAMPELA, KARI, JUHANI
分类号 D21C3/22;D21C7/12;D21C9/10;D21C11/00;G01N1/20;G01N33/34;G05B13/02 主分类号 D21C3/22
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