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发明名称
用于使记忆体阵列面积小型化之布局方法
摘要
位元线及两相同宽度之钨线路组成的线路对形成于一穿孔将形成之部份,其中该穿孔之形成系为使该位元线及该钨线路形成于规律间隔上。一用以连接至另一线路层之穿孔形成于该等钨线路之间,一钨形成之连接线路形成于该穿孔之上,以使该穿孔周围有预定安全间距。在一微影制程中,一小宽度细缝延伸于该穿孔的整个长度上,且该宽度使得该细缝不为一光阻所感知。
申请公布号
TW200518278
申请公布日期
2005.06.01
申请号
TW093118544
申请日期
2004.06.25
申请人
尔必达存储器股份有限公司;日立ULSI系统股份有限公司;日立制作所股份有限公司
发明人
渡 由布子;荒井公司;成井诚司
分类号
H01L21/8242;H01L21/768
主分类号
H01L21/8242
代理机构
代理人
何金涂;何秋远
主权项
地址
日本
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